1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM) device
2. Description of the Related Art
As the integration of a DRAM device has been enhanced, a multi-divided array structure has been adopted. That is, a memory cell array is divided into a plurality of blocks, so that a plurality of sense amplifier columns and a plurality of sub word line driven columns are provided.
Provided at cross areas between the sub word line drivers and the sense amplifier columns are sense amplifier control circuits, each including a sense amplifier (SAP) driver for pulling up PMOS sources of flip-flops of the sense amplifier columns to a write voltage and a sense amplifier (SAN) driver for pulling down the NMOS sources of the flip-flops of the sense amplifier columns to a ground voltage. Since the SAP driver is constructed by a P-channel MOS transistor and the SAN driver is constructed by an N-channel MOS transistor, each of the sense amplifier control circuits needs a large PN isolation region for isolating a P-type well for the SAP driver and an N-type well for the SAN driver (see M. Nakamura et al., "A 29ns 64Mb DRAM with Hierachical Array Architecture", IEEE Journal of Solid-State Circuits, Vol. 31, No 9, pp. 1302-1307, September 1996).
In order to reduce the PN isolation region, a semiconductor memory device wherein each of the sense amplifier control circuits is constructed by a P-type well or an N-type well has been proposed (see Japanese Patent Application No. 8-10527 filed on Jan. 25, 1996 invented by Kyoiich NAGATA et al. and published as JP-A-9-205182 on Aug. 5, 1997). This will be explained later in detail.
In the above-proposed semiconductor memory device, however, since each of the SAP drivers are constructed by a P-channel NOS transistor, the driving capability of the SAP drivers is small. Note that the current supply capability of P-channel MOS transistors is generally smaller than that of N-channel MOS transistors. In addition, since the SAP drivers are provided only in the sense amplifier control circuits formed by P-channel MOS transistors the number of the SAP drivers is decreased, so that the driving capability of the SAP drivers is decreased. Thus, the restore operation speed is decreased.